The present invention relates to a VLSI memory array with a layout that minimizes bit line loading so as to improve speed.
In memory arrays there is a delay in charging up the word lines being selected due to the conductor resistance, in the capacitance represented by the devices attached to the word line and in parasitic capacitance between the word lines and bit lines. Since the bit lines are normally metal the resistance of the bit lines is small and the capacitance represented by the attached devices is the main contributor to the bit line load. For the word lines the parasitic capacitance to each crossing bit line is relatively small so that the main load contributor is the conductor resistance and the capacitance of each device attached to the word line.
Accordingly, it is a principal object of the present invention to provide a memory array layout which considerably increases the speed of the array.